Nano-device modeling for low-power applications
VLSI physical design
Semiconductor sensors

HONOURS & AWARDS

• Organizing member of VLSI DCS 2020
• Organizing member of VLSI DCS 2021
• Organizing member of MSSND, 2019, JU
• Session Chair and coordinator in VLSI DCS 2020
• Session Chair and coordinator in MSSND 2019
• Member of IEEE Electron Device Society
• Reviewer of VLSI DCS, 2020 and MSSND, 2019

WORK EXPERIENCE

• Worked as lecturer in MSIT from July 2008 to December 2009
• Worked as Assistant Professor with AGP 6,000 from December 2009 to December 2014
• Worked as Assistant Professor with AGP 7,000 from December 2014 to March, 2022.
• Working as Assistant Professor with AGP 8,000 from April, 2022 to till date.

ADMINISTRATIVE RESPOSIBILITY

• Member of Training and Placement Cell
• Coordinator of Alumni Committee
• Member of MOOCs committee
• Member of Admission Committee
• Class Coordinator of 4th year ECE
• Former Lab In-Charge of Digital Electronics
• Lab In-Charge of Analog Electronic Circuits
• Former member of Exam Committee
• Member of Routine Committee
• Former member of Social media and Website development Committee

EDUCATION:

Doctor of Philosophy (Ph.D. (Tech)): Dept. of ETCE, Jadavpur University.
Master of Technology (M. Tech.): MAKAUT, formerly known as West Bengal University of Technology
Bachelor of Technology (B. Tech.): Institute of Engineering & Management under the University of Kalyani

PUBLISHED JOURNALS

1. Sudipta Ghosh, S Nath and S K Sarkar “Performance Study of PSO Variants and its’
Comparison with Firefly Algorithm in the context of VLSI Global Routing”, SSRG International Journal of Electronics and Communication Engineering, Special Issue, ISSN: 2348 – 8549., pp. 63-77, 2015.Peer Reviewed Journal. [I.F:0.72, SCOPUS]

2. S Nath, A K Chakravarty, Sudipta Ghosh and S K Sarkar, “FPGA Placement Optimization using Firefly Algorithm”, Advances in Industrial Engineering and Management, American Scientific Journal, ISSN: 2222-7059Vol. 6, no. 2, pp. 97-102, 2017 Peer Reviewed Journal [I.F:1.60, DOAJ Indexed]


3. Sourav Guha, Prithviraj Pachal, Sudipta Ghosh, Subir Kumar Sarkar,“Analytical model of a novel double gate metal-infused stacked gate-oxide tunnel field-effect transistor (TFET) for low power and high-speed performance”, Superlattices and Microstructures, Volume 146, 2020, ISSN 0749-6036, doi.org/10.1016/j.spmi.2020.106657. [I.F:2.658, SCI Journal]

4. Sudipta Ghosh, P. Venkateswaran, and Subir Kumar Sarkar, "Analysis of circuit performance of Ge-Si hetero structure TFET based on analytical model", Circuit World, ISSN: 0305-6120. https://doi.org/10.1108/CW-08-2020-0175, 2021. [I.F:0.875, SCI Journal]

5. Ghosh. Sudipta, Saha. Priyanka, Mukherjee. Adrija, Bose, Sayan. Venkateswaran, P., Sarkar. Subir Kumar, “Analytical Modeling of Core–Shell Junctionless RADFET dosimeter of Improved Sensitivity” Silicon (2022), 1876-9918, https://doi.org/10.1007/s12633-022-01690-y. [I.F:2.67, SCI Journal]

6. M Chanda, S Roy, Sudipta Ghosh, P Debnath, “AI/ML-based model to investigate the variability of the Fully Depleted SOI MOSFET”, Communicated to Journal of computational electronics, Springer on November 8th, 2024, DOI: https://doi.org/10.21203/rs.3.rs-5346094/v1.

7. SS Das, Sudipta Ghosh, SK Sarkar, “Study of A Heterojunction Double Gate Ferroelectric pnin Tunnel FET combining analytical modeling and TCAD simulation”, Micro and Nanostructures 196, 208003. 2024, ISSN 2773-0123, https://doi.org/10.1016/j.micrna.2024.208003.

PROFESSIONAL MEMBERSHIP

• Member of IEEE Electron Device Society since 2018 (ID: 95063254)
• Member of IEEE Solid-State Circuits Society, Kolkata Chapter since 2023.

TEACHING ASSIGNMENTS/ COURSES TAUGHT (TEACHING):
A. UG COURSE
• Analog Electronics
• Digital Electronics
• Communication Engineering & Coding Theory
• Error Control Coding
• Wireless Communication
• RADAR
• VLSI Design Automation
• Nano-electronics
• Computer Architecture

B. PG COURSE
• VLSI Physical Design
• VLSI Testing & Verifications
• Error Control Coding (SNU)

PUBLISHED CONFERENCE

1. S Nath, Sudipta. Ghosh and S K Sarkar, “A Novel Approach to Discrete Particle Swarm Optimization for Efficient Routing in VLSI Design”, 4th IEEE International Conference on Reliability, Infocom Technologies and Optimization, Noida, India, 2014.

2. Sudipta. Ghosh, S. Nath, R. Biswas, P. Venkateswaran, J. K. Sing and S. K. Sarkar, "PSO Variants and its Comparison with Firefly Algorithm in Solving VLSI Global Routing Problem," 2018 IEEE Electron Devices Kolkata Conference (EDKCON), Kolkata, India, 2018, pp. 513-518, doi: 10.1109/EDKCON.2018.8770397.

3. Sudipta Ghosh, P. Pachal, R. Kumar, S. Kundu, J. Ghosh and S. K. Sarkar, "Performance enhancement of p-n-p-n TFET with spacer induced hetero-dielctric gate oxide" 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), Kolkata, India, 2020, pp. 1-5, doi: 10.1109/VLSIDCS47293.2020.9179943.

4. Sudipta Ghosh, S. Kundu, S. Guha, J. Ghosh, P. Pachal and S. K. Sarkar, "Effect of Body Thickness on Device Performance of Graded Channel Tri-Metal Double Gate Stack Gate TFET," 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), Kolkata, India, 2020, pp. 427-431, doi: 10.1109/VLSIDCS47293.2020.9179899.

5. Sudipta. Ghosh, S. Bose, W. Anwar, M. Banerjee, P. Venkateswaran and S. K. Sarkar, "DC and Analog/RF Performance Analysis of Gate-Drain Underlapped and Channel Engineered TFET," 2022 IEEE VLSI Device Circuit and System (VLSI DCS), 2022, pp. 70-74, doi: 10.1109/VLSIDCS53788.2022.9811483.

6. Sudipta. Ghosh, A. Jana, A. K. Agnihotri, S. Kundu, D. Das and S. K. Sarkar, "DC and Analog/RF Performance Comparison of Renovated GAA JLFET Structures," 2022 IEEE VLSI Device Circuit and System (VLSI DCS), 2022, pp. 80-84, doi: 10.1109/VLSIDCS53788.2022.9811488.

7. S Misra, S Dhar, A Sarkar, S Sarkar, AS Chakraborty, S Roy, Sudipta Ghosh, “Impact of Trap Charge effects on the Performance of 2D material-based FET”, 2022 IEEE International Conference of Electron Devices Society Kolkata.

8. SS Das, Sudipta Ghosh, SK Sarkar, “Performance Analysis of a Heterojunction Dual Gate Ferroelectric Tunnel FET with Variation of Gate Stack Dielectric combination”, 2024 IEEE International Conference of Electron Devices Society Kolkata.