About

IEEE VLSI DCS-2020

2nd Int.Conference on VLSI Device, Circuit and System

Conference Record: 47293

Organized by,

IEEE Electron Device MSIT Student Branch Chapter

Focal Areas:

Components, Devices, Circuits, and Systems

Date: March 21st-22nd, 2020

Venue: Meghnad Saha Institute of Technology, Kolkata, India

http://sites.ieee.org/sb-msitceds/vlsi-dcs-2020/

Welcome to 2020 IEEE VLSI-DCS, to be held in Meghnad Saha Institute of Technology (MSIT), Kolkata, India on October March 21st-22nd, 2020. The annual VLSI-DCS conference is a premier international forum for researchers, developers and users to present and discuss the cutting edge ideas on topics related to the VLSI devices, circuits and Systems. The conference is organized by IEEE ED MSIT Student Branch Chapter. The technical program will be tailored to reflect the wide spectrum of topics and research interests shared by researchers in the fields. We invite you to submit your original contributions, not presented or published or submitted anywhere in full or in part, or not under consideration.

All the accepted and presented papers will be submitted for inclusion into IEEE Xplore after being presented in the conference.

* All the accepted and presented papers will be sent to the IEEE ffor possible inclusion in the IEEEXplore. Some of the extended version of the accepted and presented papers will be published in the special issues of the following journals,

1.Special Issue in Nanoscience & Nanotechnology-Asia, Bentham Science, Scopus Indexed https://www.benthamscience.com/journal-files/special-issue-details/NNA-SII20190415-01.pdf

2. Special issue in Journal of Mechanics of Continua and Mathematical Sciences (Emerging Sources Citation Index (ESCI)), published by IOMOCAMS http://www.journalimcms.org/

3. Special issue in International Journal of Nanoscience, World Scientific, (Emerging Sources Citation Index (ESCI)) https://www.worldscientific.com/worldscinet/ijn

4. Special Issue in Nanomaterials and Energy, ICE publishing (Emerging Sources Citation Index (ESCI)) https://www.icevirtuallibrary.com/toc/jnaen/current?=

5. Special Issue in Circuit World, Emerland Journal (ISSN: 0305-6120) (2018 Impact Factor: 1.042) http://www.emeraldgrouppublishing.com/products/journals/call_for_papers.htm?id=8719

Call For Papers

Topics of particular interest include, but are not limited to:

Track A: VLSI Devices

Device Modelling and Simulations, Optoelectronic Devices and Displays, MEMS, Sensors and Imagers, Power Devices, Deeply Embedded Devices and technology, Characterization, Reliability and Yield, Compound Semiconductors and High Speed Devices, Process and Manufacturing Technology, Memory Devices, Emerging devices, Neuromorphic Devices and Device Concepts, Low Power Devices and Circuits, Advanced CMOS and Beyond CMOS Devices, Photovoltaic Devices, Emerging natural and nature-inspired materials, Advanced CMOS and Beyond CMOS Devices for application in Microsystems, Logic synthesis and finite automata, Circuit and Device Interactions, Biodegradable and Flexible electronic Devices, Electron Devices for "More than Moore", Role of Electron Devices in Transforming Surface Transportation, synthesis and verification of integrated circuits and systems of any complexity.

Track B: Nanotechnology:

Novel nano-materials and devices, Nanobiotechnology, Nanomaterials for energy conversion, Green nanotechnology, Nano Mechanics, Carbon Nanotubes emitters, Biological applications of nanoparticles, Energy applications of nanomaterials, Nano Fabrication and Metrology, Nano Heat Transfer and Energy Information Technology, Nano Sensors, Actuators and Systems Nanobionics, Nanofluidics and Bio Chips, Organic Electronics, Organic field-effect transistors (OFETs), organic electrochemical transistors (OECTs), proton transistors.

Track C: Analog/Digital/Mixed VLSI Circuits:

Analog and Mixed Signal Integrated Circuits, Amplifiers, Filters, Comparators, Oscillators, Multipliers, PLLs, RF ICs, Voltage/Current References, Sample-And-Hold Circuits, A/D and D/A Converters, High Speed IO Interface, Energy Harvesting, Power Management, Wireless Transceivers and RF/mm-Wave Circuits, Low Power Circuits and systems, Circuits in Sub-threshold and Near threshold regime, Digital Integrated Circuits, SOC, and NOC, Linear and Non-linear Circuits, Bio Chips; MEMS/NEMS circuitry, Standalone memory circuits: DRAM, FLASH, Quantum Modeling, chaos/neural/fuzzy-logic Circuits, novel I/O circuits for advancing data rates, improving power efficiency, and supporting extended voltage applications, clocking techniques including PLLs and CDRs components such as equalizers, high-speed ADC-RX/DAC-TX, silicon photonic and optical interface circuitry.

Track D: VLSI Systems :

Embedded system: architecture, design, and software; System architectures: NoC, 3D, multi-core, and reconfigurable; Memory System; FPGA designs, FPGA based systems; CAD: synthesis and analysis, Prototyping, verification, modeling, and simulation; imagers, displays, sensors and biomedical and healthcare applications; IoT including ultra-low power, energy harvest, wearable,sensors, display, and communication devices Big Data, Machine learning Algorithm; Wireline and Optical Communications Circuits and Systems for electrical and optical communications including serial links for intra-chip and chip-to-chip interconnections,high-speed memory and graphics interfaces, backplanes, long-haul, and power line communications; flexible, printed, large-area and organic electronics. system in package, 2.5D, 3D and monolithic 3DIC, multi-die heterogeneous integration, silicon photonic interconnects and packaging, advanced assembly and bonding, embedded cooling technologies, Efficient electrical system, Reconfigurable computing, Cluster Computation, High Performance Distributed Computing (HPDC), parallel and/or distributed computing techniques, parallel processing, distributed computing systems and computer networks.

Track E: VLSI Algorithm, Design & Testing :

Analog/Mixed-Signal/RF Test, ATPG & Compression, Embedded System & Board Test, Embedded Test Methods Emerging Technologies Test, FPGA Test, Silicon Debug, Automotive Test & Safety, Built-In Self-Test (BIST) Defect & Current Based Test, Defect/Fault Tolerance, Delay & Performance Test, Design for Testability (DFT) Design Verification /Validation, Fault Modeling and Simulation, Hardware Security, Low-Power IC test , Microsystems / MEMS /Sensors Test, Memory Test and Repair, On-Line Test & Error correction, Power / Thermal Issues in Test, System-on-Chip (SOC) Test, Test Standards, Test Economics, Test of Biomedical Devices, Test of High-Speed I/O, Test Quality and Reliability, Test Resource Partitioning, Transients and Soft Errors 2.5D, 3D and SiP Test.

Paper Submission

Paper Submission Guidelines and Proceedings:

• Paper length must be maximum five pages of A4 size paper including figures and references. Its content must be original and unpublished
• Manuscript must be prepared to conform IEEE Conference format, e.g. font type, size, column, etc. Accepted paper/s must be registered and presented at the conference.
• If an author has got more than one accepted papers, each paper has also to be registered. Papers (pdf ) are to be submitted via Easy Chair Conference System. Paper Submission link: https://easychair.org/conferences/?conf=ieeevlsidcs2020

Paper review process

After submission, the paper enters into the review process. VLSI DCS 2020 research papers are reviewed using a single-blind process managed through EasyChair. A committee of reviewers selected by the Technical Committee will review the documents and rate them according to quality, relevance, correctness, and originality. The review process of research papers (full papers and short papers) for VLSI DCS 2020 will be a two-round process. Papers are reviewed on the basis that they do not contain plagiarized material and have not been submitted to any other conference at the same time (double submission). In the first round, papers are reviewed independently by a minimum of three members of the conference Technical Program Committee (TPC). No outside reviewing is used for In the first round, papers are reviewed independently by a minimum of three members of the conference Technical Program Committee (TPC). No outside reviewing is used for VLSI DCS 2020.

Registration

Member	Amount for Indian Author (INR)	Amount for International Authors (USD)
Non-IEEE Members from Academia and Industry	4000	200
IEEE Members from Academia and Industry	3500	150
IEEE Student Members (only UG) (All authors must be student)*	2500	100
Non-IEEE Student Members (only UG) (All authors must be student)	3000	150
Accompanying Person	2500	100

* as per IEEE Registration Fee Requirements

• It is mandatory for one of the authors for each paper to register in advance and present the paper for inclusion in the conference proceedings. According to IEEE's No-show policy, it is up to the discretion of the Conference Committee to allow "no shows" to be published in the IEEE Xplore Digital Library.

• To register as a student member, all the authors must be student members.

• Without formal acceptance of the paper, Deposition of Registration Fee is not allowed.

• Registration Fees will cover: Registration kits, working time Breakfast/Lunch/snacks/tea, participation certificates.

• Registration fee excludes accommodation.

• Registration fee is for a single delegate.

• Registration fee is non refundable.

• Research scholars will not be considered as any category of student.

• Registration is required for each accepted paper separately.

• If an author has more than one accepted paper, he has to register each paper separately. If co-authors want to participate, they have to register as "Accompanying Person".

• All registered authors name will be displayed in this website.

• Best papers award will be provided with certificates.

• Post-conference services as such as processing papers and then forwarding to the journals (as per journals requirements) will be handled by the Guest Editors. For Journal Publication, Guest Editors will communicate to the authors after the conference. Authors should follow the guide lines mentioned by the Guest Editors timely. If they fail to submit papers as revised version within the time limit, conference authority will not be liable for that.

• After conference, according to the feed back given by Judges/experts, papers will be grouped for journals.

• Guest editors for the journals will give call to authors for submitting the extended versions. If guest editor is satisfied then he will invite authors for uploading their papers in a particular selected journal.

It is mandatory for one of the authors for each paper to register in advance and present the paper for inclusion in the conference proceedings. According to IEEE’s No-show policy, it is up to the discretion of the Conference Committee to allow “no shows” to be published in the IEEE Xplore Digital Library.

Important Dates

( Revised due to rescheduling of the conference )

Full paper submission date: 15-April-2020 (Closed)
Notification of acceptance date: 20-June-2020
Registration of the accepted papers: 30-June-2020 (Closed)
Camera ready Submission: 30-June-2020

Tutorial & Exhibition

1. IoT Networks and Analysis Speaker: Dr. Amlan Chakraborty, Dean, AKCSIT, Calcutta University
2. VLSI Design by Verilog-A Speaker:
3. Device Modelling Speaker: Communication is in progress
4. Low Power VLSI Circuit Designs Speaker: Communication is in progress

Program Speakers

Plenary Talks:
1. Prof. (Dr.) Writam Banerjee, Pohang University of Science and Technology, South Korea
3. Dr. R.K.K. Ajeena, Babylon University, Iraq
4. Dr. Amit Banerjee , NUS, Singapore
5. Prof. A. K. Panda, IEEE EDS DL, NIST Berhampur
6. Prof. Hafizur Rahaman, Professor, IIEST-BESU

Key Note Talks:

1. Prof. (Dr.) Amlan Chakraborty, AKCSIT, Calcutta University
2. Prof. (Dr.) Debasish De, CSE Dept., MAKAUT
3. Prof. Subir K. Sarkar, Dept. of ETCE, Jadavpur University
4. Prof. Arindam Biswas, Kaji Najrul Uiversity

COMMUNICATION IS IN PROGRESS. WILL BE UPDATED SOON

Committee

Chief Patrons:
Mr. Satyam Roy Chowdhury, MD, TIG
Mr. Tapan Kumar Ghosh, Exceutive Director, TIG

Patrons: Prof. Sukumar Ray Chaudhuri, Director, MSIT
Prof. Sushanta K. Bhattacharya, Director, Academic Quality Assurance, TIG
Prof. Chandan K. Sarkar, Professor, Jadavpur University and ExChair, IEEE Kolkata Section

General Chair: Dr. Manash Chanda, Secretary, IEEE ED Kolkata Chapter and Chapter Advisor, IEEE ED MSIT Student Branch Chapter

General Co-Chair: Dr. Sudip Dogra, Former HOD, Associate Professor, Dept. of ECE, MSIT
Dr. Ansuman Sarkar, Chairman, IEEE ED Kolkata Chapter

Program Chairs: Prof. Amlan Chakrobrty, Director, AKCSIT, University of Calcutta
Prof. Debasish De, Professor, CSE, MAKAUT
Prof. Subir K Sarkar, Professor, Jadavpur University
Prof. Hafizur Rahaman, Professor, Dept. of IT, IIEST-Shibpur

Program Co-chair: Dr. Soumya Pandit, Vice Chair, IEEE EDS SRC, Region 10
Dr. Mohan Kumar, Vice-Chair, IEEE EDS Region 10

Conveners: Prof. (Dr.) Utpal Ganguly, Professor, MSIT
Prof. Joyshree Das Roy, Dean, Student Affairs, MSIT
Dr. Ambarnath Banerjee, Professor, Dept. of EE, MSIT
Dr. Chira Dutta, HOD, Dept. of ECE, NSEC
Dr. P. K. Ghosh, HOD, Dept. of ECE, TINT-Rajarhat

Technical Program Chairs: Dr. Swapnadip De, Senior Member, IEEE
Dr. Manash Chanda, Secretary, IEEE ED Kolkata Chapter and Chapter Advisor, IEEE ED MSIT Student Branch Chapter
Dr. Angsuman Sarkar, Chairman, IEEE EDS Kolkata Chapter

Organizing Chairs: Dr. Chandi Pani, Associate Professor, Dept. of ECE, MSIT
Prof. Subhra Pratim Nath, HOD, Dept. of CSE, MSIT
Prof. Subir Kr. Hazra, HOD, IT, MSIT
Dr. Monika Saha, Head, EE,MSIT

Organizing Co-Chairs: Prof. Sudipta Ghosh, Assistant Prof., Dept. of ECE, MSIT
Prof. Indrajit Das, Assistant Prof., Dept. of IT, MSIT
Prof. Biswarup Ganguly, Assitant Prof., Dept. of EE, MSIT

Publication Chairs: Prof. (Dr.) Bhargab B. Bhattacharya, IEEE Fellow, Professor, ISI
Dr. Amit Banerjee, NUS, Singapore
Dr. Arindam Biswas, Kaji Najrul University

Publicity Chair: Dr. Subhankar Majumdar, NIT, Meghalaya
Dr. Rajnish Sharma, IEEE Delhi Section
Dr. Sneha Kabra, Secretary, IEEE EDS Delhi Chapter
Dr. P. Sutisha Melon, Immediate Past Chair, IEEE EDS Malaysia Chapter
Dr. Papiya Debnath, Dept. of BSH, TINT Rajarhat
Dr. Rana Majumdar, Dept. of CSE, MSIT

Finance Chairs: Mr. Sanjay Kishore Chakraborty, TIG
Mr. Arup Mohari, MSIT

Registration Chair: Prof. Swarnil Roy, Assistant Professor, Dept. of ECE, MSIT

Registration Co-Chair: Mrs. Tanushree Ganguli, Dept. of ECE
Ms. Saheli Chatterjee, Dept. of ECE

Organizing Committee Member : Prof. Arpan Deyashi, Ex. Comm. Member, IEEE EDS Kolkata Chapter
Dr. Bikash Sharma, Treasurer, IEEE ED Kolkata Chapter
Prof. Kamalesh Sarkar, Dept. of CSE, MSIT
Prof. Subhas Mondal, Dept. of CSE, MSIT
Dr. Surajit Bari, Dept. of ECE, NIT-Agarpara
Dr. Sunipa Roy, Dept. of ECE, GNIT
Prof. Biplab Kr. Barman, Dept. of CSE, MSIT

Local Hospitality Chair: Chair, IEEE EDS MSIT SBC
Chair, IEEE MSIT SB

Local Hospitality Co-Chair: Mr. Manoj Modak, Dept. of ECE, MSIT
Mrs. Shiuly Ganguly, Dept. of ECE, MSIT
Mr. Kamalendu Langal, Dept. of ECE, MSIT

Venue & Access

Visa Information:

The Consulate of India requires a visa application form that is completed online. To access the form follow this link: https://indianvisaonline.gov.in/visa/. Click on the orange button labeled "Regular Visa Application" in the upper-left corner to begin the process. Your application must: • Display your name exactly as it appears in your passport • Include answers for all fields • Type of visa and length of validity requested must match listing on all other documentation • Be signed on the first page under the photo, and, on the second page. In order to be accepted, all signatures must:

o Match the signature in your passport o Be in the middle of the box. They cannot touch the edges of the box or run out of the box

• Include your email address on the online application. Applications missing a personal email address will be rejected by the consulate • Be printed on single-sided sheets of paper. Double-sided applications will be rejected. You must fully print the bar code on the bottom of page 1 • Your passport will be shipped back to the address indicated on your application under "Present Address." Please read the India Visa Application Guide before you begin the online visa application form.

Venue Information:
Meghnad Saha Institute of Technology
Nazirabad, Uchchepota Kolkata- 700150 West Bengal India

From Airport

From Howrah Jn

From Sealdah

Hotel Information: Link of Few nearby hotels are -
1. Hyatt Regency, JA-1 Sector III, Salt Lake City, Kolkata, India.
2. Hotel Gateway, Ruby Hospital Crossing
3. J. W. Marriot, Mathpukur, E. M. Bypass
4. Hotel Treebo
5. Many budget hotels are also available
Please find the following links for budget hotels, www.goibibo.com www.booking.com/hotels

Contact

Contact for further details :

Dr. Manash Chanda
General Chair, 2020 IEEE VLSI DCS
Advanced VLSI Design Lab,
Dept. of ECE
Meghnad Saha Institute of Technology,
Nazirabad, Uchchepota, Kolkata-700150, West Bengal, India

mail id: ieee.vlsidcs@gmail.com ( for conference related query)
manash@msit.edu.in ( for urgent query)

contact no.: +91 9830059765